Analog-to-digital converters (ADCs) are frequently used to convert analog signals into digital signals which may be provided to integrated circuits. For example, while receiving an analog input signal, a multi-bit ADC may provide a plurality of corresponding digital output signals over a parallel data bus, where each digital output signal is associated with a corresponding data bit. An integrated circuit coupled to the ADC data bus may periodically sample the individual digital output signals to obtain a digital representation of the original analog signal.
Variations in devices and board layouts can cause the individual digital output signals to exhibit different propagation delays as they pass over the data bus to the integrated circuit. Such delays can cause the digital output signals to be misaligned with each other when received by the integrated circuit. Consequently, the integrated circuit may be prevented from sampling the entire data bus until after all digital output signals have been received.
Integrated circuits such as programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs)) may require setup and hold times of several hundred picoseconds when sampling external signals received from, for example, an ADC data bus. Such times can contribute to a further lag time before the integrated circuit may sample the data bus.
When the integrated circuit samples the data bus at relatively low sampling frequencies, the various lag times associated with data bit misalignments and setup and hold times are generally negligible and do not consume significant portions of the sampling period available to the integrated circuit. However, at higher sampling frequencies, the interface between the ADC and the PLD becomes non-trivial.
For example, at sampling frequencies in excess of 1.5 GHz, the available sampling period (i.e., the time between periodic changes in the digital output signals provided by the ADC) can shrink to less than 1 nanosecond. Because a significant portion of the available sampling period can be consumed by setup and hold times of the integrated circuit, any further delays caused by misalignment of the digital output signals can limit the maximum sampling frequency of the integrated circuit. In particular, if the sampling period shrinks to less than several hundred picoseconds, misalignments in the digital output signals from the ADC may prevent the integrated circuit from reliably sampling the ADC data bus.
As a result, there is a need for an improved approach to the providing of digital output signals to integrated circuits to support high sampling frequencies offered by current ADCs.